Released in March, 2013 Lattice announces iCE40 FGPA for ultra low power applications is available for production builds. The iCE40 FPGA in the LP384 package with a 2.5 mm x 2.5 mm micro-BGA footprint is the smallest member of the expanding iCE40 family .
Lattice promotes this family as enabling designers to rapidly add new features and differentiate cost-sensitive, space-constrained, low-power products. This new small-footprint FPGA is ideal for applications such as portable medical monitors, smart phones, digital cameras, eReaders, and compact embedded systems.
The iCE40 FPGA has 384 LUT (Look Up Tables) and consumes 25 micro-watts static core power. Already one of the smallest devices in its class, Lattice is also offering a migration path to 2.0 mm x 2.0 mm for future generations.
Brent Przybus, Senior Director of Corporate and Product Marketing at Lattice Semiconductor, introduces this new Lattice FPGA:
While system footprints continue to shrink, designers must constantly search for new ways to add more functionality so they can process more information.
The iCE40 LP384 FPGA offers the perfect architecture for capturing and processing large amounts of data at hardware speeds while using very little power and board space. It deftly handles system tasks such as managing sensor interfaces, adapting to new interface standards, and offloading the CPU without requiring fully custom-designed chips.
The iCE40 FPGA costs less than 50 cents per device in multi-million unit quantities. For a price quote and availability for your prototype or production needs, please contact your local Manufacturer’s Representative or Authorized Distributor.
An overview of the features from the Lattice datasheet:
Flexible Logic Architecture
- Four devices in iCE40 Family
- LUTs – 384 to 7,680
- I/Os – 21 to 206
Ultra Low Power Devices
- Advanced 40 nm low power process
- As low as 25 μW standby power
- Programmable low swing differential I/Os
Embedded and Distributed Memory
- Up to 128 Kbits sysMEM Embedded Block RAM
Pre-Engineered Source Synchronous I/O
- DDR registers in I/O cells
- High Performance, Flexible I/O Buffer
Programmable sysIO buffer supports wide range of interfaces:
- LVCMOS 3.3/2.5/1.8
- LVDS25E, subLVDS
- Schmitt trigger inputs, to 200 mV typical hysteresis
- Programmable pull-up mode
Flexible On-Chip Clocking
- Eight low-skew global clock resources
- Up to two analog PLLs per device
Flexible Device Configuration
- SRAM is configured through:
- Standard SPI Interface
- Internal Nonvolatile Configuration Memory (NVCM)
Broad Range of Package Options
- QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options
- Small footprint package options
- As small as 2.5×2.5mm
- ROHS Compliant
- Advanced halogen-free packaging
Related Article – A Primer On Programmable Logic For FPGA, CPLD and SOC
(Photo Credit – Lattice Semiconductor)
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