Advancements in Flash Memory Technology from the Flash Memory Summit 2012
With over 50 contributing companies to the 2012 Flash Memory Summit, there are quite a few highlights to choose from. The conference began with innovative talks by keynote speakers Rob Crooke (Intel), Scott Tracy (Oracle) and Radoslav Danilak (Skyera). The consensus was that solid state technology is nearly ready for mainstream, consumer deployment.
Memory density, standardized form factors and power / performance are all meeting or exceeding the necessary metrics. Cost is still the limiting factor for true acceptance into the marketplace. But with the increasing number of cells per unit area, and utilization of external hardware for compression, this barrier will soon be breached.
For enterprise solutions, cost is not so much a factor when compared with reliability. It’s estimated the write cycle endurance needs to be increased by 10x to 100x for solid state to be dominant in the server storage market.
Addressing the storage density issue, DensBits, was recognized for “Most Innovative Technology” award for their 3 bits per cell (“TLC”) architecture.
The original Flash memory was single bit per cell (“SLC”) and recently evolved to two bits per cell or multi-level-cell architecture (“MLC”). SLC has been preferred for its robustness and greater number of read-write cycles. MLC ushered in a new lower cost memory with much higher storage capacity and density. TLC pioneered by DensBits brings together the benefits of both SLC and MLC. It has more than twice the endurance of the MLC while enjoying a 30% cost reduction compared to the SLC.
The fastest growing market for Flash memory is in the consumer mobile applications. These devices are also the most constrained in size and power consumption. To augment the performance of the silicon manufacturers, the software and drivers are being optimized to better utilize the finite number of storage locations in a Flash memory device. One issue deals with the undesirable phenomenon of “write amplification”, in which information is written to a much larger amount of physical memory than would be required by the actual size of the information.
This has two deleterious side effects – the first that less memory is available to information and that the number of write cycles per cell is increased which decrease the effective life of the device. To address this, Datalight provides a driver and file system for Windows CE devices that allows for 20x more random writes.
Another company also addressing the write cycle discrepancy between SLC and MLC is Unigen .
Typically, SLC can support a minimum of 50,000 program / erase (P/E) cycles, compared with less than 10,000 for MLC. Depending on the manufacturer, density and operating conditions the P/E delta can be as high as 35x for SLC versus MLC, and the cost up to 5x. Unigen’s award winning technology, “Endura”, allows the host device monitoring capabilities of the Flash memory to be able to proactively perform housekeeping functions and cell-level-wear which brings the MLC P/E up to the SLC levels.
Each of these advancements by themselves significantly reduces the system level cost at each density level. Implementing together where possible, greatly increases the performance at each price level. For companies producing desktop, mobile or enterprise solutions the overall net effect is a much more robust design, at lower cost and higher reliability. For the end user or consumer, these are techniques are transparent but the improvements are significant and observable.
A partial list of the sponsoring companies is provided below. For complete profiles of all the exhibitors, please go to Flash Memory Summit Exhibitor Profiles
Accelerated Memory Production (AMP)
Arasan Chip Systems
Compact Flash Assocation
DensBits Drive Savers
EMC Entertainment Storage Alliance
Kingston Tech Co
Maxwell Technologies, Inc.
Nimbus Data System
OCZ Technology Group
Smart Storage Systems
TAEC Memory Products
Toshiba TAEC Storage Products