Stylus Compiler Upgrade Available For ABAX2 SpaceTime Technology FPGA From Tabula

In a continuing move to help make network infrastructure systems more responsive to applications’ dynamic needs, Tabula, Inc. announced today the availability of version 2.7.1 of its Stylus compiler supporting its ABAX2 P-Series of 3D programmable logic devices (3PLDs). Stylus 2.7.1 further eases design of complex high-bandwidth systems with the addition of support for the hardware description and verification language SystemVerilog.

To help accelerate the development of high-performance applications, the software also features new design examples showing how to utilize Spacetime technology with its many-ported memory blocks and how to build high-performance, small-footprint finite state machines (FSM) using ROM structures. This release also includes a 1 giga-samples per second Fast Fourier Transform (FFT) IP core demonstrating the digital signal processing potential of the ABAX2 family of devices.

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The new capabilities and design kits introduced in the Stylus 2.7.1 release include:

SystemVerilog support:

• Addressing the increasing customer demand for a combined design and verification language, Tabula’s Stylus compiler can now process code written following SystemVerilog syntax. This capability not only increases the supported application domains, but also prepares the path for the future use of assertion-based design debug.

Soft IP cores:

• A high-performance 1 Gsps FFT IP core is now available on the Tabula IP Management System . This core can be configured for transforms of 1K, 2K, 4K, 8K, 16K or 64K points.

Design examples:

•  A 12-ported RAM block design example showing how to express many-ported memory blocks and manage port access ordering in a Spacetime-based fabric.
•  A ROM-based finite state machine design example to illustrate how Spacetime enables new approaches to sequential logic design ideally suited to high-performance datapath systems.

More about Stylus compiler:

Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture, unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.

Availability:

Stylus version 2.7.1 is available now for download from Tabula Customer at no-charge.

(Image Credit – Tabula )

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